Search results for "Gate oxide"
showing 10 items of 11 documents
Effect of humidity on the hysteresis of single walled carbon nanotube field-effect transistors
2008
Single walled carbon nanotube field-effedt transistores (SWCNT FETs) are attributed as possible building blocks for future molecular electronics. But often these transistors seem to randomly display hysteresis in their transfer characteristics. One reason for this is suggested to be water molecules adsorbed to the surface of the gate dielectric in this study we investigate the thysteresis of SWCNT FETs at different relative humidities. We find that SWCNT FETs having atomic layer deposited (ALD) Hf0 2 -Ti0 2 .- Hf0 2 as a gate dielectric retain their. ambient condition hysteresis better in dry N2 environment than the more commonly used SiO 2 gate oxide.
Negative differential resistance in carbon nanotube field-effect transistors with patterned gate oxide.
2010
We demonstrate controllable and gate-tunable negative differential resistance in carbon nanotube field-effect transistors, at room temperature and at 4.2 K. This is achieved by effectively creating quantum dots along the carbon nanotube channel by patterning the underlying, high-kappa gate oxide. The negative differential resistance feature can be modulated by both the gate and the drain-source voltage, which leads to more than 20% change of the current peak-to-valley ratio. Our approach is fully scalable and opens up a possibility for a new class of nanoscale electronic devices using negative differential resistance in their operation.
High-Speed Memory from Carbon Nanotube Field-Effect Transistors with High-κ Gate Dielectric
2009
We demonstrate 100 ns write/erase speed of single-walled carbon nanotube field-effect transistor (SWCNT-FET) memory elements. With this high operation speed, SWCNT-FET memory elements can compete with state of the art commercial Flash memories in this figure of merit. The endurance of the memory elements is shown to exceed 104 cycles. The SWCNT-FETs have atomic layer deposited hafnium oxide as a gate dielectric, and the devices are passivated by another hafnium oxide layer in order to reduce surface chemistry effects. We discuss a model where the hafnium oxide has defect states situated above, but close in energy to, the band gap of the SWCNT. The fast and efficient charging and discharging…
Electrical and structural characterization of metal-oxide-semiconductor capacitors with silicon rich oxide
2001
Metal-oxide-semiconductor capacitors in which the gate oxide has been replaced with a silicon rich oxide (SRO) film sandwiched between two thin SiO2 layers are presented and investigated by transmission electron microscopy and electrical measurements. The grain size distribution and the amount of crystallized silicon remaining in SRO after annealing have been studied by transmission electron microscopy, whereas the charge trapping and the charge transport through the dots in the SRO layer have been extensively investigated by electrical measurements. Furthermore, a model, which explains the electrical behavior of such SRO capacitors, is presented and discussed. © 2001 American Institute of …
Statistical Analysis of Heavy-Ion Induced Gate Rupture in Power MOSFETs—Methodology for Radiation Hardness Assurance
2012
A methodology for power MOSFET radiation hardness assurance is proposed. It is based on the statistical analysis of destructive events, such as gate oxide rupture. Examples of failure rate calculations are performed.
Origin of the substrate current after soft-breakdown in thin oxide n-MOSFETs
1999
In this paper is presented an experimental investigation on the origin of the substrate current after soft-breakdown in n-MOSFETs with 4.5 nm-thick oxide. At lower voltages this current shows a plateau that can be explained with the generation of hole-electron pairs in the space charge region and at the Si-SiO2 interface, and to carrier diffusion between the channel and the substrate. At higher voltages the substrate current steeply increases with voltage, due to trap-assisted tunneling from the substrate valence band to the gate conduction band, which becomes possible for gate voltages higher than the threshold voltage. Measurements on several devices at dark and in the presence of light, …
Reduction of thermal damage in ultrathin gate oxides after intrinsic dielectric breakdown
2001
We have compared the thermal damage in ultrathin gate SiO2 layers of 5.6 and 3 nm thickness after intrinsic dielectric breakdown due to constant voltage Fowler-Nordheim stress. The power dissipated through the metal-oxide-semiconductor capacitor during the breakdown transient, measured with high time resolution, strongly decreases with oxide thickness. This is reflected in a noticeable reduction of the thermal damage found in the structure after breakdown. The effect can be explained as the consequence of the lower amount of defects present in the oxide at the breakdown instant and of the occurrence of a softer breakdown in the initial spot. The present data allow us to estimate the power t…
Anodized Ti-Si Alloy as Gate Oxide of Electrochemically-Fabricated Organic Field-Effect Transistors
2013
Organic field-effect transistors were fabricated using an electrochemical route. The dielectric oxide was grown by anodization of a Ti:Si alloy, while 3,4-polyethylenedioxythiophene has been employed as a semiconducting polymer. OutputI-Vcharacteristics showed a transistor effect dependent on dielectric thickness. Fitting between I-V measurements and theoretical simulations in the triode region confirmed the presence of a conduction path through the polymer which degrades the electrical characteristics of the devices.
Heavy-ion induced single event effects and latent damages in SiC power MOSFETs
2022
The advantages of silicon carbide (SiC) power MOSFETs make this technology attractive for space, avionics and high-energy accelerator applications. However, the current commercial technologies are still susceptible to Single Event Effects (SEEs) and latent damages induced by the radiation environment. Two types of latent damage were experimentally observed in commercial SiC power MOSFETs exposed to heavy-ions. One is observed at bias voltages just below the degradation onset and it involves the gate oxide. The other damage type is observed at bias voltages below the Single Event Burnout (SEB) limit, and it is attributed to alterations of the SiC crystal-lattice. Focused ion beam (FIB) and s…
Current Transport Mechanism for Heavy-Ion Degraded SiC MOSFETs
2019
IEEE Transactions on Nuclear Science, 66 (7)